We all know that among the different inverter typologies, the H-bridge is the most efficient one, since it does not necessitate the use of center tap transformers, and allows the use of transformers with two wires. The results become even better when four N-channel mosfets are involved.
With a two wire transformer connected to an H-bridge means the associated winding is allowed to go through the push pull oscillations in a reverse forward manner. This provides better efficiency as the attainable current gain here becomes higher than the ordinary center tap type topologies.
However better things are never easy to get or implement. When identical type mosfets are involved in an H-bridge network, driving them efficiently becomes a big problem. It is primarily due to the following facts:
As we know an H-bridge topology incorporates four mosfets for the specified operations. With all four of them being N-channel types, driving the upper mosfets or the high side mosfets becomes an issue.
This is because during conduction the upper mosfets experience almost the same level of potential at their source terminal as the supply voltage, due to the presence of the load resistance at the source terminal.
That means the upper mosfets come across similar voltage levels at their gate and source while operating.
Since as per the specs, the source voltage must be close to the ground potential for efficient conduction, the situation instantly inhibits the particular mosfet from conducting, and the entire circuit stalls.
In order to switch the upper mosfets efficiently they must be applied with a gate voltage at least 6V higher than the available supply voltage.
Meaning if the supply voltage is 12V, we would require at least 18-20V at the gate of the high side mosfets.
The proposed H-bridge inverter circuit having 4 n channel mosfets tries to overcome this problem by introducing a higher voltage bootstrapping network for operating the high side mosfets.
N1, N2, N3, N4 NOT gates from the IC 4049 are arranged as a voltage doubler circuit, which generates about 20 volts from the available 12V supply.
This voltage is applied to the high side mosfets via a couple NPN transistors.
The low side mosfets receive the gate voltages directly from the respective sources.
The oscillating (totem pole) frequency is derived from a standard decade counter IC, the IC 4017.
We know that the IC 4017 generates sequencing high outputs across its specified 10 output pins. The sequencing logic shuts subsquently as it jumps from one pin to the other.
Here all the 10 outputs are used so that the IC never gets a chance of producing incorrect switching of its output pins.
The groups of three outputs fed to the mosfets keep the pulse width to reasonable dimensions. The feature also provides the user the facility of tweaking the pulse width that’s being fed to the mosfets.
By reducing the number of outputs to the respective mosfets, the pulse width can be effectively reduced and vice versa.
This means the RMS is tweakable here to some extents, and renders the circuit a modified sine wave circuit ability.
The clocks to the IC 4017 is taken from the bootstrapping oscillator network itself.
The oscillating frequency of the bootstrapping circuit is intentionally fixed at 1kHz, so that it becomes applicable for driving the IC4017 also, which ultimately provides about 50 Hz output to the connected 4 N-channel H bridge inverter circuit.
The proposed design can be much simplified as given here: